1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having fundamental cells such as a gate array or an embedded array type semiconductor integrated circuit device composed of a plurality of CMOS transistors and a method of manufacturing the semiconductor integrated circuit device using the fundamental cells.
2. Description of the Prior Art
A gate array or an embedded array type semiconductor integrated circuit device (or a large scaled integrated circuit LSI) in which a desired circuit is formed by connecting a plurality of fundamental cells respectively composed of a plurality of transistors or the like with each other through lines has been recently used. In this semiconductor integrated circuit device, it is required to heighten an integration degree of the transistors and improve the function of the device, elements of the semiconductor integrated circuit device such as a transistor have been downsized, and a distance between lines has been shortened.
FIG. 1(A) is a plan view of a fundamental cell of a conventional CMOS type gate array. In FIG. 1, 1 denotes a fundamental cell, the fundamental cell 1 is composed of a pair of p-channel field effect transistors TP1 and TP2 and a pair of n-channel field effect transistors TN1 and TN2. A large number of fundamental cells having the same configuration as that of the fundamental cell 1 are arranged on a semiconductor substrate in a lateral direction (or an X direction) and a longitudinal direction (or a Y direction).
The transistor TP1 is composed of a gate 2A formed on the semiconductor substrate through a gate insulating layer (not shown), and a pair of impurity diffused layers 3A and 4A formed on a pair of surfaces of the semiconductor substrate placed on both sides of the gate 2A. The gate 2A is made of a conductive material and is formed in a laid T shape. Also, a back gate 5A formed by diffusing impurities in a surface portion of the semiconductor substrate is arranged on one side (an upper side in FIG. 1A) of the impurity diffused layer 3A. The impurity diffused layers 3A and 4A function as a source and a drain of the transistor TP1.
The transistor TP2 is composed of a gate 6A formed on the semiconductor substrate through a gate insulating layer (not shown), and the impurity diffused layer 4A and an impurity diffused layer 7A formed on a pair of surfaces of the semiconductor substrate placed on both sides of the gate 6A. The gate 6A is formed in a T shape directed inversely to the gate 2A of the transistor TP1. The impurity diffused layers 4A and 7A function as a source and a drain of the transistor TP2. Also, a back gate 8A formed by diffusing impurities in a surface portion of the semiconductor substrate is arranged on one side (a lower side in FIG. 1A) of the impurity diffused layer 7A. In this case, the impurity diffused layer 4A is also an element of the transistor TP1.
The transistor TN1 is arranged at a position adjacent to the transistor TP1. The transistor TN1 is composed of a gate 2B formed on the semiconductor substrate through a gate insulating layer (not shown), and a pair of impurity diffused layers 3B and 4B formed on a pair of surfaces of the semiconductor substrate placed on both sides of the gate 2B. The gate 2B is formed in symmetry to the gate 2A of the transistor TP1. Also, a back gate 5B is formed on a surface of the semiconductor surface placed on one side (an upper side in FIG. 1A) of the impurity diffused layer 3B.
The transistor TN2 is arranged at a position adjacent to the transistor TP2. The transistor TN2 is composed of a gate 6B formed on the semiconductor substrate through a gate insulating layer (not shown), and the impurity diffused layer 4B and a impurity diffused layer 7B formed on a pair of surfaces of the semiconductor substrate placed on both sides of the gate 6B. The gate 6B is formed in symmetry to the gate 6A of the transistor TP2. Also, a back gate 8B is formed on a surface of the semiconductor surface placed on one side (a lower side in FIG. 1A) of the impurity diffused layer 7B.
In FIG. 1(A), a plurality of marks + respectively denote a wiring grid at which a line of a first layer (first wiring layer) formed on the fundamental cell 1 and a line of a second layer (second wiring layer) formed on the fundamental cell 1 cross over each other. The wiring grid is arranged on a central line of each of the impurity diffused layers 3A, 3B, 4A, 4B, 7A and 7B and the back gates 5A, 5B, 8A and 8B. The lines arranged on the fundamental cell 1 is designed by using a computer-aided design (CAD) system. That is, positions of the lines are determined in the CAD system to connect the wiring grids with each other through the lines.
For example, in the fundamental cell 1 shown in FIG. 1(A), a maximum of ten lines passing in the longitudinal directions (or the Y direction) can be formed as the lines of the first layer, and a maximum of five lines can passing in the lateral directions (or the X direction) can be formed as the lines of the second layer. In this case, a pitch between lines in the first layer is the same as that in the second layer.
FIG. 1(B) is a plan view showing a bulk pitch between candidates (respectively indicated by a symbol .quadrature.) for each of positions at which contact portions for connecting the impurity diffused layers 3A, 3B, 4A, 4B, 7A and 7B and lines formed above the fundamental cell 1 are formed. In the CAD system, positions at which contact portions are actually formed are selected from the candidates for the positions according to a circuit to be formed. As shown in FIG. 1(B), each of the contact portions is formed at a grid crossing point.
FIG. 2 is a plan view of a two-input NAND circuit 9 formed by using the fundamental cell 1. In this case, five lines (from a first line to a fifth line) extending in the X direction are formed as the lines of the second layer (not shown) above the fundamental cell 1.
The gates 2A and 6A are connected with lines 31 and 32 of the first layer through the contact portions 41 and 42 and are connected with second and fourth lines (signal input lines) of the second layer through contact portions 56 and 57 for the lines of the first and second layers. Also, the gates 2A and 2B are connected with a line 34 through the contact portions 48 and 49, and the gates 6A and 6B are connected with a line 36 through contact portions 50 and 51.
The impurity diffused layers 3A and 7A and the back gates 5A and 8A are connected with a line 33 of the first layer through contact portions 43, 44, 45 and 46 and are connected with a fifth line (a power supply line) of the second layer through a contact portion 59. The impurity diffused layers 4A and 7B are connected with a line 35 through contact portions 47 and 52 and are connected with a third line (a signal output line) of the second layer through a contact portion 58. The impurity diffused layer 3B and the back gates 5B and 8B are connected with a line 37 through contact portions 53, 54 and 55 and are connected with a first line (a power supply line) of the second layer through a contact portion 60.
However, in the conventional semiconductor integrated circuit device described above, there are following drawbacks.
First, no excessive line is arranged above the fundamental cell. Therefore, in cases where a second fundamental cell and a third fundamental cell placed on both sides of a first fundamental cell are connected with each other through a line, it is required that the line takes a long way around the first fundamental cell. Therefore, the line is lengthened, and there is a probability that the degradation of a signal transmitting through the line occurs and a noise occurs in the signal.
Secondly, in cases where a line of the first layer and a line of the second layer are connected with each other, it is required to use two wiring grids. FIGS. 3(A) and 3(B) are respectively a cross-sectional view showing the connection between the gate 2A and a line 95 of the second layer. In FIGS. 3(A) and 3(B), 91 denotes an insulating layer arranged between a line of the first layer and a line of the second layer. Also, 31A denotes a connecting element arranged to prevent a disconnection of a line caused by a change of a positional difference between the contact portions 41 and 56. As shown in FIG. 3(A), in cases where the gate 2A is connected with the line 95 of the second layer, assuming that the contact portion 56 connecting the line of the first layer and the line of the second layer is formed on the contact portion 41 connecting the fundamental cell and the line of the first layer, a height of a projecting portion of the insulating layer 92 increases, and a disconnection of a line formed on the insulating layer 92 easily occurs. Therefore, as shown in FIG. 3(B), positions of the contact portions 41 and 56 are determined not to place the contact portion 56 connecting the line of the first layer and the line of the second layer above the contact portion 41 connecting the fundamental cell and the line of the first layer.
Thirdly, in cases where a region on one fundamental cell is used as a connecting region (or a wiring channel) in which other fundamental cells are connected each other, a transistor utilizing rate .alpha./(.alpha.+.beta.) in an LSI chip is lowered. Here, .alpha. denotes the number of all fundamental cells, and .beta. denotes the number of fundamental cells used as wiring channels.
FIG. 4 is an explanatory view of an example of a transistor utilizing rate in the conventional semiconductor integrated circuit device. In FIG. 4, 10A denotes a group of fundamental cells used as an output transistor circuit, and the output transistor circuit is composed of five fundamental cells 1. Five signals are, for example, output from each fundamental cell of the transistor circuit 10A. 10B denotes a group of fundamental cells used as an input transistor circuit, and the input transistor circuit is composed of five fundamental cells 1. Four signals are, for example, input to each fundamental cell of the transistor circuit 10B. 10C denotes a group of fundamental cells used as a wiring channel. Here, three lines except two power supply lines can pass through each of the fundamental cells 10A, 10B and 10C.
In cases where twenty lines connect the group of fundamental cells 10A and the group of fundamental cells 10B, seven fundamental cells (3*6+2) are required as the wiring channel. In this case, a transistor utilizing rate is low because the transistor utilizing rate is about 51% (10/17*100.congruent.51).